RISC-V has owned embedded and microcontroller for years. The argument against it at server and HPC has been simple: no open-ISA core publishes credible single-thread performance numbers. The Dubhe-100 is a direct answer: SPECint2006 of 15/GHz, 15-stage pipeline, 6-wide superscalar out-of-order execution, full RVA23 profile compliance. StarFive declares servers and HPC as the design center. That is a first for an openly licensable RISC-V core.
RVA23 compliance is the operative detail. It is the RISC-V International ratified profile for application processors -- Vector and Vector Crypto extensions included -- meaning the toolchain and OS ecosystem assumptions are standardized rather than per-vendor. The 512-entry 6-way ROB and 256-entry physical register files for both integer and FP/vector put the microarchitecture in the same class as SiFive's P870 and Tenstorrent's Ocelot. Cluster-level frequency scaling and core-level power states make multi-chip integration tractable without custom firmware negotiation. HPM support with micro-architecture-level counter access means teams can instrument real workloads before tape-out rather than after.
ISA selection for a new server SoC now includes a licensable open option with published SPECint2006. For teams that were deferring RISC-V because the toolchain investment could not be justified against an unproven performance claim, the Dubhe-100 puts a concrete number on the table. ARM's royalty-per-chip model for server silicon has a named challenger with licensable IP and a SPECint2006 baseline for the architecture review meeting.