Synopsys announces production-ready AI-powered digital and analog EDA flows for Samsung SF2 (second-generation 2nm) and SF3 (third-generation 2nm) at SAFE Forum 2026, alongside an expanded certified interface IP portfolio. This is not new PDK support. It is a joint certification that removes the tool-process risk from the design-start decision on Samsung's leading-edge nodes.
When a team commits a program to a next-generation process, the first risk they evaluate is not mask cost or yield: it is whether the EDA tools have been validated on that PDK. A miscalibrated extraction engine or uncertified IP block discovered at tapeout review adds weeks to the schedule and often forces a foundry switch or respin. Joint Synopsys-Samsung certification of the full digital-analog-signoff flow flips that risk: design starts on SF2 and SF3 can proceed with confidence in the tool-process combination rather than with the design team carrying qualification on its own schedule. The AI-powered optimization layers across Fusion Compiler and PrimeTime mean teams are not just getting a certified starting point; they are getting an AI-optimized PPA result as the baseline.
The teams that benefit most are groups that have been tracking Samsung 2nm but holding back on resource commitment until the EDA stack was proven on the node. That waiting ends after SAFE Forum. Cadence will certify its own flows on SF2 and SF3 within quarters; the competition for design starts on Samsung's newest processes is now fully open. Design-services firms that were charging for manual tool-process qualification on these nodes see that margin compress as foundry onboarding packages absorb the work.