SYNTLOG benchmarked against Xilinx Vivado across 101 FSM descriptions spanning small to super-huge (thousands of states, hundreds of I/Os), and the results are not close. In area-driven mode, SYNTLOG uses 45% to 66% fewer LUTs than Vivado's area baseline at every size class. Its delay-driven mode produces shallower logic depth than Vivado's default synthesis mode. Runtime is faster by one to two orders of magnitude. On the huge and super-huge circuits, SYNTLOG finishes in minutes. Vivado does not terminate after hours.
The tool is architecture-independent, meaning synthesis decisions are not locked to a specific FPGA family's primitives at the point of logic mapping. It also includes embedded functional validation as part of synthesis, so the output is verified before the designer receives it. That pairing matters: faster synthesis is useful, but faster synthesis with built-in validation removes a separate verification step from the flow entirely.
For FSM-heavy designs, the resource numbers have direct cost consequences. A 60% LUT reduction is not incremental optimization; it is the difference between fitting a design on a smaller, cheaper FPGA or running at higher density without routing congestion. The embedded validation also shifts the correctness check left into synthesis rather than leaving it to downstream simulation.
The broader pattern here is consistent with what happened in routing (Quilter) and RTL optimization (SynAct, GoalEvolve): specialized open-source tools are beating commercial synthesis on specific problem classes by not being constrained by the same generality requirements. Vivado has to handle everything. SYNTLOG handles FSMs, and handling that one thing correctly turns out to require a completely different approach.