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SignalTakibi

Takibi Checks 600 Random RISC-V Privilege Programs in Lockstep

Takibi compares a RISC-V core against a reference across 600 randomized privilege programs and proves the test can catch a hidden interrupt.

Thesis connection

Randomized comparison turns subtle processor privilege behavior into a repeatable test before the core reaches a board.

#risc-v#testing#verification#eda
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Takibi now runs 600 randomized programs through its 32-bit RISC-V core and a reference model in lockstep, comparing their state after each step. The programs start in machine, supervisor, or user privilege modes and vary interrupt routing, counters, timers, and permission bits. All 600 passed.

The count alone isn't the evidence. The test prints which target mode and interrupt cause each run reached, and a negative test confirms that it detects a deliberately hidden supervisor interrupt. Building the board simulation also caught a separate language-boundary bug: the core called its timer input time, which Verilog reserves as a keyword, so the input is now named mtime.

Processor privilege bugs live in combinations that directed tests rarely enumerate. Random generation helps only when coverage shows which combinations ran and an injected fault proves the checker notices. Takibi now has both, which makes the next 600 programs useful evidence instead of a larger green number.

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