The Tensor Memory Accelerator project now publishes the test record behind its 17.86 megabytes-per-second result on a DE10-Lite field-programmable gate array (FPGA). Its four-word prefetch moves a 2,048-byte matrix transpose in 114.7 microseconds, 2.88 times faster than the serialized baseline. More important, the repository includes the eight cocotb simulation profiles, random seed, source hashes, observed scenarios, and corruption control used to check that number.
The regression drives the real direct memory access (DMA) engine and synchronous dynamic random-access memory (SDRAM) controller through their public interfaces. A Python reference checks 46,992 DMA transactions and 206,376 memory readbacks, while an independent pin-level model checks memory commands and timing. Deliberately flipping one response bit proves the checker can fail, rather than merely recording a clean run.
The board measurement still covers one tile in one memory bank, and four-word prefetch is 23 percent slower on a sparse column gather. Those limits make the evidence more useful, because a buyer can see where the headline stops applying. Accelerator teams should publish this kind of result bundle with every performance claim; otherwise the benchmark is marketing material, no matter how many decimal places it carries.