Tenstorrent is treating the virtual platform as an executable contract between RISC-V hardware and software teams. Vayavya Labs has modeled security enclave registers, system management logic, DMA engines with secure zeroing, boot and fuse infrastructure, and cryptographic hardware since 2024. Software and validation teams can now find integration failures before the physical device exists instead of waiting for first silicon.
The models use SystemC/TLM and Vayavya's CSML library, which provides an open, Accellera-compatible path alongside a commercial simulation target. The latest Open Chiplet Harness security enclave platform runs on two independent simulation targets. That matters because a model tied to one simulator becomes another handoff artifact; a portable model can become shared validation infrastructure across architecture, firmware, and verification.
Tenstorrent should measure how many boot, security, and driver defects move from post-silicon bring-up into pre-silicon regression over the next two tapeouts. RISC-V teams that still start serious firmware integration when boards arrive are accepting a schedule risk that executable subsystem models can now remove.