Terracotta makes a new DRAM capability deployable by configuring the memory controller instead of redesigning the interface and controller together. That changes memory innovation from a silicon coordination project into a programmable integration task.
The DDR5-based framework defines custom command extensions for DRAM vendors and a controller that system designers can program after silicon ships. Across processing-in-DRAM, maintenance, subarray parallelism, and latency reduction, the authors report more than 96% of the performance benefit of custom implementations. The cost is 0.03% processor area, 0.56% power, and 0.6% to 3.2% DRAM energy overhead. The source is public, which gives architecture teams a concrete substrate for reproducing those tradeoffs.
A week spent testing Terracotta against one planned memory feature is now cheaper than another vendor-specific controller fork. If the MICRO 2026 results hold across real controllers, programmable DRAM command paths will appear in at least one commercial server platform by 2028.