Hardware prefetchers are tuned for coverage, which means they prefetch aggressively and waste a substantial fraction of memory bandwidth on data that never gets used. In multi-tenant datacenter environments, that wasted bandwidth has a direct cost. Themis is a hardware-software interface that lets software annotate specific data pages as bad prefetch candidates via unused page-table entry bits, and lets the hardware read those annotations at runtime to suppress the prefetcher for those pages.
The result is a 40% reduction in useless prefetch requests, with IPC speedups of 4.1% for BOP, 3.1% for SPP+PPF, and 1.4% for Pythia. No ISA changes, no binary modifications. The profiling step runs offline; page-table hints are written once and applied at runtime. Any existing hardware prefetcher can be paired with Themis without changes to the prefetch logic.
The performance numbers are secondary to the interface shape. Hardware prefetchers have been black-box policies tuned at design time. Themis treats the prefetcher as a component with a software-visible input surface: the page table. Once that surface exists, prefetch policy becomes something an OS scheduler or hypervisor can optimize per-tenant, not just per-chip. That is a structurally different programming model for memory hardware.
If this interface makes it into a future CPU ISA or OS specification (the paper is from Google, Microsoft Research, Cornell, and UW, the teams who write those specs), the beneficiaries are OS engineers and hypervisor developers. The prefetcher stays the same. The software layer gains a lever it did not have before, and per-tenant memory bandwidth accounting becomes a solvable problem.