Chiplet-based DNN accelerators fail late when thermal violations surface after the architecture is locked. The standard flow: pick a partition, implement it, run thermal analysis, discover violation, re-partition. ThermoDSE breaks that cycle by making thermal and yield first-class constraints inside the design space exploration loop rather than checks that run after search completes. The result is 3.5x improvement in EDIY (energy times delay times inverse yield) over the Simba baseline, and faster convergence than simulated annealing and RL baselines evaluated in the paper.
The mechanism is a unified simulation framework that integrates fine-grained task modeling, chiplet granularity, and inter-chiplet communication with real thermal and area budgets. The search prunes thermally infeasible configurations early and can favor yield-efficient chiplet counts and granularities that a thermally-naive search would skip. This is the first framework that includes all these factors together, which means prior work (Simba included) was optimizing a partial objective.
For teams designing AI accelerators on chiplet substrates, thermal violation is one of the most expensive late-stage discoveries: it triggers re-floorplanning, sometimes changes chiplet count, and at minimum requires thermal interface redesign. If ThermoDSE's models calibrate to your specific process and packaging stack, running DSE with thermal constraints inline is strictly better than running them sequentially. The open question is generalization beyond the chiplet architectures and workloads in the evaluation. Teams building similar systems should test it; the framework is on arXiv and the specific EDIY metric is well-defined enough to reproduce.