Topstitch can now select a named field from a packed SystemVerilog structure and read named values from an enumeration. Packed structures group several signals into one fixed-width port. Before this change, software assembling a chip design had to treat that port as numbered bits, which made a harmless field reorder look like valid but wrong wiring.
The tool now asks the SystemVerilog compiler for the resolved type, including fields hidden behind package aliases and arrays. It then slices the correct bits by name and carries compiler errors back to the caller. Modules and packages are imported in one compilation, so a generated connection sees the same definitions as the design it is wiring.
Named selection gives hardware generators a useful property software developers expect from typed interfaces: an incompatible edit fails where the connection is made. Our bet is that within a year, serious chip-assembly tools will be judged on whether they preserve this kind of language meaning, not merely whether they can concatenate ports.