Researchers at the University of Illinois Urbana-Champaign just demonstrated monolithic 3D silicon chips fabricated at under 200 degrees C using junctionless transistors. That is the exotic-materials constraint being removed. For two decades, monolithic 3D integration looked better than TSV-based 3D stacking on paper but stayed there, because getting silicon layers to bond at low enough temperatures without destroying the metal interconnects below required carbon nanotubes, 2D semiconductors, or metal-oxide materials that nobody had in a production fab. Silicon was always the obvious answer; nobody could make it work below 400 degrees C. UIUC made it work below 200 degrees C.
The mechanism is junctionless transistors: source, channel, and drain are all the same doping type, so no high-temperature p-n junction formation is needed. UIUC deposited single-crystal silicon membranes 10 nm or less thick via a wafer-scale roll transfer process. The layers align with nanometer precision, giving connectivity density 10x to 100x beyond what through-silicon vias can manage. The bottom layer uses n-type silicon, the top uses p-type, linked vertically to form complementary logic. Critically, junctionless transistors also simplify the process flow, which improves yield in ways TSV assembly cannot.
The consequence is that the fabrication path for monolithic 3D now runs through existing silicon manufacturing infrastructure, not a greenfield exotic-material line. Packaging houses and interposer suppliers that positioned 3D stacking as the permanent density answer are now defending against a technology that requires no new material ecosystems. The open question is process maturity: UIUC demonstrated the physics, not a production node. But the EDA implication arrives before the fab implication. Tools designed around planar silicon with post-fab 3D attachment now need to handle true monolithic vertical integration, where timing, power, and thermal models span layers that were grown, not bonded. If silicon monolithic 3D reaches pilot production in the next five years, the first design teams to validate EDA flows against it will own the early process window.