Vision generative AI hardware has been a follower. Models drove architecture; hardware chased. This paper from Tselepi et al. names that as a structural problem: progress in vision GenAI has been driven by output quality metrics, with accelerators redesigned after the model architecture settled rather than co-designed alongside it. The result is measurable as energy inefficiency and latency headroom left on the table across every platform in the survey.
The survey maps four generative model families (diffusion, autoregressive, flow-based, hybrid) against seven accelerator platforms and quantifies parameter cost and energy efficiency of each combination. The cases where performance falls below what the hardware can theoretically deliver are not edge cases; they are the norm. The gap between what current accelerators do and what they could do under proactive co-design is the implicit argument for shifting the design loop.
The edge angle is the sharpest part. Datacenters can throw hardware at reactive design gaps; edge deployments cannot. Autonomous vehicles, agricultural sensors, and mobile devices run vision generative models under strict power and latency budgets with no room to overspec. The paper maps the seven platforms against edge constraints explicitly. Teams building accelerators for edge vision inference in 2026 who are still accepting model architecture as given input to the chip design process are accepting a penalty the survey now has numbers for. The question is whether SoC roadmap cycles are short enough to act on it before the model families shift again.