The first working triple-stacked nanosheet CFET at a 42nm gate pitch was presented today at the VLSI Symposium (Paper T1.1, Donghoon Hwang et al.). It is the tightest gate pitch and highest nanosheet count demonstrated for a 3D stacked FET. CFET mass production is still targeted for 2031, but the gap between "feasibility vehicle" and "scalable towards production pitch" just closed meaningfully.
The mechanism of interest is not the transistor itself; it is the planning horizon. SoC architects and EDA vendors operate on 5-7 year tool and IP roadmaps. The question of whether CFET at industrially relevant pitches could be fabricated was, until this paper, open. At 60nm gate pitch, Intel had working CFETs. At 48nm, TSMC's work shown earlier at this symposium advanced the envelope. The 42nm triple-stack by Hwang et al. shows the stacking approach holds at pitch values that map to the node after A14. That gives architecture teams something concrete to plan against rather than a roadmap projection.
The EDA consequence is direct: CFET introduces vertically stacked complementary devices, which breaks assumptions in standard-cell layout tools built for planar and nanosheet flows. Synopsys, Cadence, and Siemens have all started CFET-aware research programs, but customer investment decisions in CFET-oriented IP have lagged because "first silicon at aggressive pitch" was still a claimed future state. That qualification is now retired. Expect EDA vendor investment in CFET-native cell libraries and PnR support to accelerate over the next 18 months as foundry PDK engagement moves from research to customer NDA.