External PHY chips are a recurring BOM problem in industrial IoT and edge AI designs. A 10/100 Ethernet MAC-only MCU requires a separate PHY, a separate crystal or oscillator, and a separate routing topology for the MII/RMII interface. A USB 2.0 high-speed application requires a separate HS PHY with its own power supply. And any application running inference or display needs PSRAM, which means another SPI or parallel bus, another power rail, and another BOM line. WCH's CH32V407 and CH32V467 fold all three into one die: integrated 10/100 MAC+PHY, 480 Mbps USB 2.0 HS host PHY, and up to 8MB PSRAM, at 200 MHz on their QingKe V3V RISC-V core with RVV vector extensions.
The supply chain consequence is concrete. An industrial edge node that previously required the MCU, a separate LAN8720 or similar PHY, a USB3300-class HS PHY, and an external PSRAM now fits those functions on one die and one BOM line. That is three components removed from procurement exposure, three component footprints removed from the PCB, and three independent sourcing relationships consolidated. At the volumes where this matters -- contract manufacturing runs in the tens of thousands -- that compression shows up directly in lead time risk and unit economics.
The WCH QingKe V3V core delivers 4.11 CoreMark/MHz, above a typical Cortex-M4, with RVV vector extensions for AI acceleration. The RVV presence is the tell that WCH is positioning this part for edge inference workloads, not just connectivity. Whether the on-chip PSRAM bandwidth is sufficient for the model sizes those workloads require is a design constraint that teams will hit at evaluation. The right comparison is not whether 8MB PSRAM is enough for all use cases -- it is whether it is enough to run the inference workload without an external chip. For many edge AI applications at this tier, it will be.