Web888 now saves a field-programmable gate array (FPGA) resource report even when the later placement and routing step fails. A design that has exhausted the chip's logic or memory often fails during routing, and the old build discarded the report that showed which module consumed those resources.
The Vivado script now runs synthesis first, opens that completed result, and writes resource-use reports for the whole design and each module. Only then does it start implementation, the stage that places logic on the chip and connects it. Continuous integration (CI) uploads the synthesis reports with an always condition, so an implementation failure cannot hide them. The change is 21 lines, but it preserves the evidence needed to decide whether to shrink a filter, move a table into block memory, or choose a larger device.
FPGA builds can take long enough that a failure with no retained diagnostics wastes a second tool run before anyone can fix the design. Web888 should add a machine-readable resource budget next, so CI can reject a growing module before routing becomes impossible. Teams using Vivado can copy this split now and archive synthesis reports independently of the final bitstream.