xcbrup can now replace the program stored inside a field-programmable gate array (FPGA) design without running logic synthesis again. That matters for soft processors, where changing firmware used to send an otherwise unchanged hardware design back through Yosys before engineers could produce an updated configuration file.
The tool learned how Xilinx 7-series memory blocks pack a hexadecimal program image into bit planes. A learn command rebuilds every initialization bit and compares it with the routed design, refusing to continue if the layout doesn't match. A patch command then writes the new memory values into FPGA assembly (FASM), the text representation of the configured chip. The older Yosys path remains available as an independent check.
openXC7 verified the result three ways on an XC7S50 device: the direct patch matched the Yosys output byte for byte, matched a complete nextpnr routing run, and read back 335,872 memory bits correctly from hardware. Teams with a processor inside an FPGA should add this path beside the full build, compare both outputs in continuous integration, and use the faster patch for firmware iterations only after that comparison stays clean.